1. Field of the Invention
The present invention relates to an ESD protection apparatus to be installed in a semiconductor integrated circuit chip in order to protect a semiconductor integrated circuit from electrostatic discharge (ESD) and to a method for fabricating the protection apparatus.
2. Description of the Prior Art
A conventional ESD protection apparatus in the CMOS process generally protects a semiconductor integrated circuit using a MOSFET transverse parasitic bipolar transistor by releasing the electric current in the transverse direction lateral direction in a silicon substrate. On the other hand, the ESD protection apparatus has been required to be further miniaturized since the number of pins to be mounted on one chip has been increased sharply following the recent acute requirement of development of semiconductor integrated circuits made finer.